资源列表
Pipeline-3.zip
- Verilog codes for pipelined processor,Verilog codes for pipelined processor
clock
- 时钟分配电路，输入为时钟信号CLK，输出为信号F0~F5，这六个信 号中只允许有一个为高电平，F0、F2、F4的持续时间为2个CLK，F1、F3、F5的持续时间为4个CLK。 -A clock distribution circuit, the input clock signal CLK, the output signal F0 ~~ F5, the six signal only allowed to have a high level, F0, F2, F4 duration o
FPGA-training-experience
- 至芯科技FPGA工程师就业培训班学生培训心得，让你对FPGA有更好的了解-FPGA engineer employment training courses students training experience to the core technology, so you have a better understanding of the FPGA
bit4_4
- 利用verilog语言编写的控制4个继电器开关动作的程序， 采用RS232通信-Verilog language program control the four relay switch action RS232 communication
a2012..41
- 粤嵌开发箱的简单测试代码——显示数字5s后并自动更换。-Guangdong embedded development box simple test code- display digital 5s and automatically replaced.
Binary_VGA_Controller
- terasic的DM9000A模块源码，使用nios2做以太网应用的应该会用到-terasic the DM9000A module source, use nios2 do Ethernet applications should be used
Chapter7-Sample
- SAA7113 ＦＰＧＡ开发实例，非常经典-The SAA7113 FPGA development examples, very classic
lbq3
- 滤波器的verilog代码 主要是对算法的折叠 有原先的4个加法器四个乘法器变成2个加法器两个乘法器-Filter verilog code folding algorithm 4 adder four multipliers into two adders and two multipliers
design
- static timing analysis and timing paths
arm-fpga.rar
- arm fpga 通讯驱动代码 arm fpga 通讯驱动代码,arm fpga comunicate
pci
- PCI硬核源代码,支持33.3M的时钟频率,支持IO模式和内存模式的PCI操作-PCI operation of the the PCI hard core source code, support 33.3M clock frequency to support IO mode and memory mode
EDAjiaotong
- EDA交通灯 红黄绿左拐，四个等，不同时间，还有计时器-EDA red yellow and green traffic lights turn left, four different times, there is a timer