资源列表
simplepwm
- quartusII调试，简单的pwm信号输出，FPGA初学者入门程序，高手勿进-quartusII debugging, not into simple pwm signal output FPGA beginner program, master
DDS
- 这是一个用EP2C5T144的FPGA制作的DDS信号发生器，输出信号波形可变，幅度可调，缺点是信号频率略低，带有电路图-This is a used EP2C5T144 FPGA produced DDS signal generator, the output signal waveform variable adjustable amplitude, the disadvantage is that the signal frequency is slightly lower, with
shift-register
- 一个8位的左右移位寄存器电路，输入为时钟信号CLK，方向控制信号D， 输出信号为每个寄存器的状态。 -An 8-bit left and right shift register circuit, the input of the clock signal CLK, the direction control signal D, the output signal of the status of each register.
Pipeline-and-FIFO
- Pipeline and FIFO的FPGA设计-Pipeline and FIFO FPGA design
Key_Xiaodou_Delay
- Verilog语言，Quartus II开发环境，按键延时消抖IP。-Verilog language, Quartus II development environment, key delay shake away IP.
decoder83
- 一个83译码器，使用VRILOG写的，对初学者很有用-A 83 decoder
shizhongfinal
- 通过按键控制的数字钟，verilog代码-a diagil clock design by verilog
VHDL_FIR
- VHDL设计的14阶FIR滤波器，根据已给出滤波器系数以及验证程序，选用Altera的EP2S60F484C3器件进行设计。-VHDL design of the 14-order FIR filter design, according to the filter coefficients as well as the verification process has been given the EP2S60F484C3 selected Altera devices.
BCD-youxianbianma
- 优先编码器，通过VHDL语言实现BCD优先编码的功能-Priority encoder BCD priority encoder function through VHDL language
shuzizhong
- 在单片机上实现数字钟，时分秒的显示以及整点报时功能。-Realize single-chip digital clock, hour, minute and second of the display, as well as the whole point timekeeping function.
adio_encoser_and_decoder.zip
- digital audio conversion logic,digital audio conversion logic
ISP1362
- 友晶公司的开发源代码，使用起来比较方便，学习FPGA的都会用到-Terasic development source code, it was easier to use, will be used for learning FPGA