资源列表
PWM_OUT
- 这是一个EP2C5T144的FPGA产生PWM信号到LED上控制LED的亮度的源程序，可以通过按键来改变占空比，带有电路图:)-This is a PWM signal to control the brightness of the LED to the LED source a EP2C5T144 the FPGA button to change the duty cycle, with the circuit diagram :)
ISE_lab14
- 以前的xilinx公司的软件的FPGA的实验程序4-Xilinx company s previous software FPGA experimental program
uart-code-(Verilog)
- uart 源码 Verilog CPLD -uart code Verilog CPLD
RS-232
- RS-232发送接受模块，测试好用，满足一般要求-RS-232 transmit and receive modules, easy to use test, meet the general requirements
STA_plan_routing
- 关于数字逻辑设计中静态时序分析和布局布线相关的资料。-Static timing analysis in digital logic design and layout information.
SDRAM-design-FPGA-altera
- SDRAM design FPGA altera-SDRAM design FPGA altera.
VHDL_LAPS
- 简化LAPS协议，对发送的数据包进行封装、传输和接收，，包含FCS是对整个LAPS帧进行CRC校验。-Simplify LAPS protocol, encapsulation, transmission, and receiving the transmitted data packet, containing FCS is performed on the entire LAPS frame CRC.
Virtex-5_FPGA_yonghuzhinan
- Virtex-5相关文档，适合于开发初期的了解工作。-Virtex-5 document, suitable for the development of the understanding of the early work.
DDS
- 一个DDS的程序，很有用，可以产生频率可控的正弦波-A DDS program is useful, can produce controllable frequency sine wave
ultimate_crc_latest.tar
- CRC循环校验源代码，来源于OPENCOREs,用于数字电路中的错误检验。-CRC Cyclic check source code from the OPENCOREs, the error checking used in the digital circuit.
stepmotornios
- Altera SOPC系统和Nios II处理器实现的一个简单的步进电机驱动系统。
pipelined_reconfig_multiplier
- parallel pipeline reconfigurable multiplier