资源列表
Audio_Codec_WM8731.rar
- 这是一个控制WM8731的IP。通过SOPC直接可以挂在总线下。,This is a the WM8731 control IP. Can be linked through the SOPC directly under the bus.
convert
- Program that convert verilog-file of Xilinx FPGA to PicoBlaze instactions-Program that convert verilog-file of Xilinx FPGA to PicoBlaze instactions
VGA_INTERFACE
- 用Verilog HDL写的VGA控制器，基于Avalon总线-The VGA Controller based on Avalon
SRC
- SVGA显示的SRC文件，全面详细，方便上手，是学生赞不绝口的好代码-SRC file SVGA display, comprehensive and detailed, easy to use, full of praise for the good code for students
SIMTUT_TB.VHD
- 用StateCAD设计一个“串进并出的加法器”状态机，并使用StateCAD测试激励生成器设计测试激励，验证该状态机，掌握完整的StateCAD设计流程.
sdram
- sdram controller.verilog
DE1-Practice-VGA-display-
- 用altera的fpga设计的DE1开发板作为硬件平台实现VGA显示，verilog实现的，8种色彩，作为fpga驱动vga液晶的入门。DE1实践之VGA显示（8bit色彩）-Altera fpga design with the DE1 board as a hardware platform development VGA display, verilog implementation, 8 colors, as the introduction to fpga driver vga LCD
30TLC5615
- TLC的运用编程，对数位的了解，用TLC进行模拟-Something about TLC so you can use it easy
task2
- Sample multiplexor 8 to 1
rs232
- 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
Synplify.Premier.v9.6.2.with.I
- Synplify.Premier.v9.6.2.with.Identify.3.0.2 crack,Synplify.Premier.v9.6.2.with.Identify.3.0.2 crack
altera_avalon_checksum7.2
- 7.2版的altera_avalon_checksum.altera提供的自定义组件的例子-7.2altera_avalon_checksum