资源列表
FPGAluojidaima
- 16通道逻辑分析仪，100M，FPGA代码，包括FIFO，dram，usb等-16 channel logic analyzer, 100 m, the FPGA code, including FIFO, DRAM, usb, etc
silutongbufujieqi
- 介绍了有代表性的较简单的四路同步复接器系统程序设计。- Introduced has the representative simple four group synchronized multiple connection system programming.
bono_evb_cpld_1.2.rar
- sources of CPLD (fpga) from freescale i.MX27 Avanced Designe System Develpment Kit board,sources of CPLD (fpga) from freescale i.MX27 Avanced Designe System Develpment Kit board
PIC
- 这个是基于Proteus仿真软件锁搭的，内容是关于PIC16F877单片机交通灯仿真！ 希望对大家有用！-This is based on the Proteus simulation software lock ride, the contents of the traffic lights on PIC16F877 microcontroller simulation! I hope useful!
365counter
- 使用Electronics Workbench 5.0电子仿真软件(EWB)设计的365进制计数器。-Using electronic simulation software Electronics Workbench 5.0 (EWB) design a counter(365 BCD).
degree
- This code is use to display angles in degrees on LCD.
MX29LV160DTB
- 29LV160或8/16位16Mbit的FLASH防真模型，Verilog语言编写-29LV160 or 8/16 anti-FLASH 16Mbit the true model, Verilog language
viterbi
- verilog code for viterbi encoder and decoder
clock
- 本程序实现数字钟系统，有整点报时功能，可显示切换年月日，定时功能-Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function
512_RSA
- 512位RSA VHDL 算法,使用了蒙哥马利模乘算法，该程序写的有些麻烦，但是对于初学者学习是够了。-512 bit RSA VHDL algorithm,it is open cores.it is very good for beginers to study.
c23_RS_decoder
- 精通verilog HDL语言编程源码9——RS(204,188)译码器的设计-Proficient in verilog HDL source programming language 9- RS (204188) decoder design
xapp616
- A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx-A. Huffman implementation reference desig n in both VHDL and Verilog is provided by the Xili nx