资源列表
Q12.1Crackx86
- Altera Quartus 12.1 Software Patch
ddr_sdram_controller_vhdl.rar
- DDR SDRAM控制器的VHDL代码已经测试,DDR SDRAM controller VHDL code
standard_sim_tb
- xilinx CTC IPcore(encoder 和 decoder）的标准测试，未经信道加噪-the standard test of xilinx CTC IPcore (encoder and decoder) , without the channel with noise
Mul16
- 16位高速乘法器,采用booth编码，华莱士压缩，超前进位加法器求和完成-16-bits Multiplier
61i_parallel_multiplier_v6_0_vhdl
- multiplyer In Xilinx ISE
Example-b8-5
- 四态的VCD文件，参数在0/1/X/Z之间变化，没有信号的强度信息-The four state VCD file, parameter changes between 0/1/X/Z, no intensity information of the signal
DPLL(VHDL).rar
- 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开,The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
fenpinjishuqi
- 本文档包括实现分频的方法以及奇数分频偶数分频的verilog代码 经测试可用-This document includes methods to achieve divide and even the odd divider divider verilog code used by the test
用FPGA实现SRAM读写控制的Verilog代码
- 用FPGA实现SRAM读写控制的Verilog代码-SRAM FPGA implementation using Verilog code to read and write control
8255mode1
- 基于vhdl语言微机并口8255方式1的实现源代码-Vhdl language computer-based way of a parallel implementation of 8255 source code
CH1VHDL 数字电路参考书所有程序1
- VHDL 与数字电路设计程序参考书所有程序 1-VHDL and digital circuit design process all the procedures a reference book
iic
- 用vhdl实现iir总线仿真 对于vhdl初学者很有帮助-Iir bus simulation using vhdl