资源列表
CS5361_DAT
- CS5361 ADC 驱动程序,其中还有时钟部分,这里是数据采集部分. 使用VerilogHDL编写,在Libero中编译,使用Actel芯片测试通过.-CS5361 ADC drivers, of which there are clock parts, here is the data collection using VerilogHDL written, compiled in Libero using Actel chip test.
keshe
- 也许是一个比较有用的数码骰子。。经过随机数然后进行数码管显示-Perhaps a more useful digital dice. . After a random number and then the digital display
lab4_project
- lab4中基于ISE的lab4实验的程序源代码，这里使用的是ISE13.4的版本-lab4 in ISE-based lab4 experimental program source code, here is the version ISE13.4
RUILI
- 均匀相位的瑞利衰落信道matlab仿真程序，并附有详细注释-Uniform phase Rayleigh fading channel matlab simulation program, together with detailed notes
3-8-decoder
- 三八译码器,用Verilog HDL语言描述，包含文件说明以及波形截图-3-8 decoder using Verilog HDL language descr iption, including documentation and waveform capture
8-1-mux
- 八选一数据选择器，Verilog HDL语言描述，包含文件说明和波形截图-8-1 MUX, Verilog HDL language descr iption ， contains the file descr iption and waveform capture
10010sequece-detector
- 序列发生器，Verilog HDL语言描述，包含文件说明和波形截图-Sequence generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
M=15generator
- 模15序列发生器，Verilog HDL语言描述，包含文件说明和波形截图-mod15 generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
voter
- 少数服从多数表决器，Verilog HDL语言描述，包含文件说明和波形截图-Majority voter, Verilog HDL language descr iption, contains the file descr iption and waveform capture
mux4
- 改程序实现的四选一数据选择器的工程，该程序为自己编程，并经过仿真验证此程序正确-Reform program to achieve the four selected a data selector works, the program for their own programming, and through simulation this procedure correctly
ds_test12
- 在Verilog语言下用FPGA驱动DS18B20，带数码管显示，带LED报警，有报警值调整功能。这个是本人调过的，原版调通代码没改的，绝对能跑通。建议用QuatusII全编译后看一下RTL图就能理解程序是怎么工作的。-A Demo of DS18B20 on FPGA.
curriculum_design_v2
- 课程设计，数字频率计源代码，用Verilog HDL写的-Curriculum design, digital frequency meter source code, written using Verilog HDL