资源列表
BlazeNoC_QoS-master
- BlazeNoC_QoS：支持QoS的可重配置片上网络路由，有很高的性能。此代码包括完整的Xilinx ISE的工程，可以很方便地修改和移植。-BlazeNoC_QoS: QoS-reconfigurable chip network routing, a high performance. This code includes a complete Xilinx ISE project, can be easily modified and transplantation.
Virtex-5--user-manuals-chineses
- xilinx virtex-5 中文用户手册 介绍了virtex5 的内部结构 功能和使用示例 完整清晰 -Chinese virtex5 user manual describes the function and use of the internal structure of an example of complete and clear
Verilog
- virtex-5 库声明代码 verilog版本 包含完整的原语实例化代码-virtex-5 library declaration code verilog version contains the complete primitive instantiation code
jishuqi
- 各进位计数器，包括16位，10位，4位都齐了-The binary counter, including 16, 10, 4 all here
ds_test12
- HDL语言初始化 ds18b20，数码管温度显示，蜂鸣器报警-HDL language initialization ds18b20, digital temperature display, buzzer alarm
VGA
- verilog HDL语言写的VGA驱动代码-HDL write VGA driver code
hard
- 在Quartus中，利用FPGA例化的存储器实现程序的BOOTLOADER的搬移-In Quartus, the use of FPGA case of memory to achieve the program' s move BOOTLOADER
a_vhdl_can_controller
- 使用VHDL语言编写的CAN总线控制器程序，经过编译和波形仿真验证。可以为大家提供一个参考。-Using VHDL language CAN bus controller program, compiled and waveform simulation. Can provide a reference for everyone.
digital-lock
- 数字锁的详细设计流程以及VHDL仿真过程和结果，附有源码-The detailed design process digital lock and VHDL simulation process and results, with source code
jiaoyan
- Verilog编写的crc16校验程序，为大家通信校验提供一种可靠的方法-Verilog prepared crc16 checksum procedure for everyone to provide a reliable communication method validation
UART_FIFO
- Verilog编写的串口配合FIFO的代码，对大家学习串口和FIFO有一定帮助-Verilog prepared with FIFO serial code, we learn the serial port and FIFO have some help
welecome_key
- Verilog编写的按键控制串口的发送数据，接收的数据通过数码管显示-Verilog prepared by the buttons control the serial port to send data, receive data through the digital display