资源列表
Rendering primitives
- Some 2D graphic rendering in VHDL: - Line - Draw a line - Circle - Draw circle - BitBLT - Draw a rectangle - Sine and cosinus lookup tables - Rotation - Rotate line
source
- SDRAM控制器的fpga实现，非常好的例子sdram控制器-sdram contoller for you
second
- 实现spartan3E板上的流水灯，是用verilog语言写成的，简单易用-Water board to achieve spartan3E lights, is written in verilog language, easy to use
Mux81a
- 8选1数据选择器 VHDL文件 数电很有用的-8 to 1 Data Selector VHDL file useful for digital circuits
sixuanyi
- 四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D-four elected a selector, the importation of four, Output 1. When NM = 00 A at the election when NM = 01 am when the election NM B = C 10:00 when the election NM = 11:00 election D
ADC0832
- AD0832 AD转换程序，功能完全通过测试，备注非常详细，KEILC编程，通用性强-AD0832 AD converter, fully functional test, notes, very detailed, KEILC programming, versatility
SPI_VHDL
- SPI串口的内核实现（vhdl）,可以用qII等软件直接加到FPGA或者CPLD里面.-the SPI Serial Kernel (vhdl) can be used directly qII software foisted CPLD or FPGA inside.
add
- 一位全加器源码实现了MAX及其一系列器件实现全加的功能-A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian
94117c05d50c
- Its a clock Sequence for DDR3 Controller.Hope u find it useful
33-square-root
- 使用VHDL语言实现33位平方根进位选择加法器，能满足在500M时钟下正确工作，使用DB测试，并通过前仿。-Using VHDL language 33 square root carry select adder, to meet in the 500M clock work correctly, use the DB test, and through imitation.
SVPWM-VHDL
- fpga永磁同步电机矢量控制系统，包括死区等模块-fpga foc
Caculator
- 基于Verilog语言编写的简易计算器，实现了加减法的运算，有模块和约束文件。-Verilog language based on simple calculator, to achieve the operation of addition and subtraction, there are modules and constraint files.