资源列表
MULT
- 用VERILOG实现乘法器功能，通过仿真验证-With VERILOG multiplier function is verified by simulation
UART
- 用verilog实现串口通信程序，通过仿真验证-Serial communication program, is verified by simulation with verilog
labs_system_verilog_testbench
- system verilog testbench 对应代码。-labs for system verilog testbench
add
- FPGA VERILOG 加法器，数码管显示-FPGA VERILOG the Adder, digital tube display
digita_clock
- spartan 3 7 segment clock display
usb_in
- 基于VHDL的USB读写程序 只供参考哦 -VHDL-based USB reader program
Clock_module
- 使用Verilog语言编写的建议时钟，并能通过按键配置时钟。-Recommended clock using Verilog language, and through the buttons configuration clock.
div
- FPGA VHDL实现 时钟分频一秒 fpga-The FPGA VHDL clocks divide one second
trrfic_lamp
- FPGA设计的交通灯，四个状态自动跳转，用的数码管显示，不带紧急情况-FPGA design, traffic lights, four states automatically jump with digital display, without emergency
baud_gen
- 运用VHDL语言，实现串口收发程序中的波特率设置的子程序，可以将该子模块加载到主程序中。-VHDL language, set the baud rate of the serial transceiver subroutine, this sub-module is loaded into the main program.
fengmingqi
- FPGA VHDL实现 分频器一秒 fpga-The FPGA VHDL clocks divide one second
Msignal_text
- M序列发生器，长度可调，输出为有符号数，性能稳定。-M-sequence generator, adjustable length, the output for a number of symbols, and stable performance.