资源列表
ram
- CPU中一个部件——ＲＡＭ的编程，运用ＦＰＧＡ，硬件描述语言-CPU a part-- RAM programming, using FPGA, hardware descr iption language
LED
- FPGA VHDL实现 点亮LED灯 VHDL实现-FPGA VHDL lit LED lights VHDL implementation
VHDL-uart
- 本程序应用VHDL语言，详细描述了RS232串口协议，包括发送，接收，波特率的产生，模块化编程，对于初学者尤为有宜！-The program in VHDL language, the detailed descr iption of the RS232 serial protocol, including sending, receiving, and baud rate generation, modular programming, especially for beginners sho
ad_control
- 用verilog实现对AD7656的控制，包括AD的启停、数据的读入。-control the AD7656 to work properly
NIOS_UART
- FPGA QUARTUS 异步串行口通讯模块程序，常用模块。-FPGA QUARTUS sync serial communication routine,uart.
AD7793
- 运用VHDL语言，实现AD7793芯片的采样程序和SPI的通讯程序，可以将该子模块加载到主程序中。-VHDL language to achieve the AD7793 chip sampling procedures and SPI communication program, this sub-module is loaded into the main program.
Ram_FIFO
- 同步fifo 适合学生使用 深度为十六 适合刚入门的学生联系堆栈-sys fifo
AntGlitch
- 运用VHDL语言，实现脉冲采集的滤波子程序，利用打两拍进行毛刺滤波，可以将该子模块加载到主程序中。-The use of the VHDL language, to achieve the the pulse collected filtering subroutine utilize playing two beats glitch filtering, the sub module is loaded into the main program.
MUX_8
- 用verilog实现串口通信程序，通过仿真验证-Serial communication program, is verified by simulation with verilog
Four-bit-full-adder
- 四位全加器，是自己编写的，如有错误，请原谅-I have written four full adder, is subject to error, please forgive
xufeng_cdr
- 软件CDR 设计，在LATTICE 平台上验证通过，含说明PPT。Lattice soft cdr-Lattice soft cdr
duogongnengshuzizhong
- 多功能数字钟VHDL源文件,采用动态显示方式,6个数码管-Multifunction digital clock VHDL source files, dynamic display, six digital tube