资源列表
VHDL_Ethernet
- VHDL实现的以太网测试仪器，可以根据配置生成各种模式的以太网数据报文，并对接收到的以太网数据进行统计。-VHDL realization of Ethernet test instrument can generate a variety of modes depending on the configuration of Ethernet data packets, and receives Ethernet data statistics.
BCD-counter
- 一个2位的BCD码十进制加法计数器电路，输入为时钟信号CLK，进位 输入信号CIN，每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT，输入时钟信号CLK用固定时钟，进位输入信号CIN. -A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output s
DS18B20
- 本源码用verilog实现对DS18b20温度传感器的时序控制，使DS18b20能正常工作，获得温度数据-The source verilog of DS18b20 temperature sensor timing control, so DS18b20 can work to obtain temperature data
camero_driver
- 驱动并初始化OV7670摄像头，并在FPGA上做初步的数据处理和存储，用Diamond2.0软件进行仿真和调试的配置-Driver and initialize OV7670 camera on FPGA preliminary data processing and storage, Diamond2.0 software simulation and debugging configuration
Debussy-learning
- Debussy仿真软件使用方法及配套的实例代码。很详细的介绍了Debussy软件的使用方法，结合Modelsim来使用-Debussy simulation software use and supporting examples of code. Very detailed descr iption of the use of Debussy software, combined with Modelsim to use
RS232C_Verilog.rar
- rs232c 的verilog hdl 源码，验证可用，利于大的系统集成。,The codes of verilog hdl for RS232C, its useful characteristic can be integrated in a big system.
ISE_lab17
- FPGA experimental program xilinx company s previous software -FPGA experimental program xilinx company s previous software
counter
- 将50MHz时钟信号分频为1Hz,对1Hz方波信号进行计数，并利用4连体数码管进行动态显示-50MHz clock signal at a frequency of 1Hz, to count the 1 Hz square wave signal, and using 4 Siamese digital tube dynamic display
MUSIC_1
- 一首一定要爱你的歌在FPGA中演奏，非常的好玩-Must love you a song played in the FPGA, very fun
ulpiereport.tar
- 开源的ULPI IP核，可用于USB3300芯片的开发-openSource ULPI IP core which could be used for USB3300 chip development
qsys_design
- altera Qsys使用说明，陪了一个简单的例子，供参考-the altera Qsys Instructions accompany a simple example, for reference
DMA
- DMA controller VHDL code entity dma is generic ( ADDR_WIDTH : integer := 16 -- default value DATA_WIDTH : integer := 16 -- default value ) port ( RESET_L : in std_logic CLK : in std_logic DRQ_L : in std_logic DMAA