资源列表
uart_txd_rxd.zip
- 将接收到的并行数据转换成串行数据来传输。消息帧从一个低位起始位开始，后面是5~8个数据位，一个可用的奇偶位和一个或几个高位停止位。接收器发现开始位时它就知道数据准备发送,Converting the received parallel data into serial data to transmit. The message frame from a low start bit is followed by 5 to 8 data bits, parity bit, and one of th
100vhdl
- 用vhdl语言学习100例，适合硬件编程的初级学者。-The vhdl language learning 100 cases suitable hardware programming junior scholars.
firOK
- 一个已经经过验证正确的数字滤波器源码，希望大家喜欢-One has been proven correct digital filter source code, hope you like! !
03~chapter-02-dft
- Slides from book "VLSI Test principles"
Verilog
- RAM ,IFFO实现字节的存储器设计，经过验证-RAM, IFFO bytes of memory design, proven
nonsythasizable8pointfft
- A Fast Fourier Transform(FFT) is an efficient algorithm for calculating the discrete Fourier transform of a set of data. A DFT basically decomposes a set of data in time domain into different frequency components. DFT is defined by the following equa
zhengxiansanjiao
- 用Verilog实现正弦波和三角波，验证过的，功能正确-Sine wave and triangular wave with Verilog and verified correct function
64
- 利用FPGA实现的脉宽测试技术,基于VHDL,测试误差为时钟周期-FPGA implementation of pulse-width test clock cycle technology, based on VHDL, test error
VHDL-Files
- 北京化工大学EDA实验源代码。内含有显示8位学号，显示电压值控制，显示时钟，还有一次大实验，用到包的调用。-Beijing University of Chemical Technology EDA experiment source code. Contains 8 student number is displayed, display the voltage value of the control to display the clock, there is one big experi
Xilinx_DLL
- Xilinx_FPGA的时钟产生模块，对应Xilinx公司Virtex、Virtex-E等比较低端的器件。能够产生2倍频和级联4倍频-generate 2X clock and 4X clock in low-end Xilinx FPGA devices
UART_Universal
- 基于FPGA逻辑单元设计的通用异步串行接口设计UART，波特率参数化，模块分解易懂易上手-General UART Design based on FPGA logic
FPGA_Divider
- FPGA实现除法器的功能，并行逻辑计算，输出结果为商和余数。适用于FPGA内部无IP核等的低端FPGA器件上。-Function of Divider based on FPGA logic,output result includes the quotient and remainder. This function is applied to the low-end FPGA devices