资源列表
Hexto7
- Hexadecimal to 7 segments
10-binary-counter
- 使用verilog实现10进制计数器功能,可以实现Quartus仿真，含任意进制计数器程序-10 binary counter using verilog implementation function, can realize Quartus simulation program with an arbitrary binary counter
soccorrobo
- SOCCER-ROBOT DESIGN ON FPGA source code. The robot is triangle width 20 cm. height 15 cm. have 3 motor and control by L298 chip.
caideng
- 实现彩灯控制循环点亮，通过muxplu2测试通过。可以直接使用-achieve lit lanterns control cycle through muxplu2 test. Direct access
EDA-digital-clock
- 显示时、分、秒，有手动校时功能，计时过程具有报时功能-Display hours, minutes, seconds, manual timing function, timing processes with chime
resetdelay
- 这是一个复位延时程序，对复位信号进行定时的延时，确保抖动多产生的信号误差-This is a reset delay procedures, the timing delay of the reset signal, to ensure jitter and more signals generated error
TPA81_pic24f
- 我已经得到了相当多的要求与I2C总线部分的PIC24教程。-I’ve gotten quite a few requests for the I2C bus section of the PIC24 tutorial. PIC I2C
jiaotongdeng
- 用VHDL做的一个交通灯的实验，这个程序的主要功能是：有8个灯，主路和支路分别增加了转弯的灯；有救护车，当救护车按键为高电平时，产生救护车中断，主路和支路红灯亮。同时数码管在当前计数值和全0之间循环显示；有喇叭voice；-Use VHDL to do a traffic light experiment, the main functions of this program: There are eight lights, the main road and slip roads increa
1
- 基于VHDL的1602驱动程序，采用状态机的方法编写-Based on VHDL-1602 driver, prepared by the state machine
wishbone
- wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
adders-verilog
- all adders verilog code
DDS
- 基于直接序列合成的vhdl语言 基于直接序列合成的vhdl语言-Synthesis based on direct sequence vhdl language synthesis based on direct sequence vhdl language synthesis based on direct sequence vhdl language