资源列表
sr_flip_flop.ZIP
- I upload a source code for SR flipflop here.
tabla_q.edn
- DESIGN TRBGVAERNR FRAKAEF AKEF A DKF
UART-Communication
- Xilinx FPGA UART communication code
s
- nios的hello world代码，重要的是泡在了sram上，作为存储器-nios in the hello world code, it is important to soak in the sram, as a memory
sdr
- numerically controlled oscillator-numerically controlled oscillator...
audiofiles
- audio file on virtex
VHDL_FFT2
- 基于FPGA设计的FFT模块文件，用VHDL语言编写！！已通过测试，希望对大家有用-FFT designs based on FPGA module file, using VHDL language! ! Has passed the test, hope for all of us! ! !
cic_decimator
- system generator 环境中构造cic数字滤波器 抽取-construct cic digital filter extraction system generator environment
JTAG
- JTAG Verilog source code
filter1
- 题为基于CSD编码的FIR数字滤波器设计.该滤波器具有线性相位,系数减半.采用VHDL语言编写.是我们EDA课程的作业,得了优.希望对大家有用-Entitled based on CSD code FIR digital filter design. That the filters have linear phase, coefficient half. Using VHDL language. Is the EDA program operations, got excellent. Hop
uart
- UART的控制程序，可以很好的控制UART的运行-UART control program, a good control of the UART operation
serial
- 串行转并行的VHDL源代码，结构化编程，学习模块化编程和实用性都很大。-Serial transfer parallel VHDL source code, structured programming, modular programming and practical learning are great.