资源列表
niosII_system_cpu
- cpu代码，可在ISE或quartus下完成调试-cpu code, can be accomplished under the ISE or Quartus debugging
FPGA-on-the-LED-display-control
- FPGA对LED显示器的控制，包括设计方法，部分源代码和结果-FPGA on the LED display control
yejingdeng
- 液晶时钟 连线方式：将拨码开关的第6脚拨向"ON"方向，即给lcd供电-Crystal clock attachment: dial 6 feet of code switch to "ON", namely to LCD power supply
Blocking_and_Non_blocking
- Verilog Blocking and Non Blocking
register
- it is source code of 32 bit register and testbench for tht register written in verilog.
FIFO
- here is realized simple FIFO stack in vhdl. very simple example, but very helpful.
ycbcr.v
- full pipelined RGB->YUV 420 converter, Xilinx/Altera implementable
osd
- 攒人品上传多年工作积累代码。主要功能是OSD图形控制的代码。经过验证，可以综合。-Save the character to upload the accumulation of many years of working code. The main function is to control the OSD graphics code. Proven, can be integrated.
Avalon_VGA
- vga显示彩色图像ip，alter开发板-vga display color image,vhdl,quartus
yuequyanzou
- 乐曲演奏，使用quartusⅡ软件平台实现乐曲‘梁祝’的演奏。-Musical quartus Ⅱ software platform to realize the song ' Butterfly Lovers' playing.
Mini-project-code1
- 4 bit booth multiplier is uploade
magnitude
- Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algori