资源列表
project-05
- Project05.zip Memory.hdl
FPGA
- FPGA面试笔试题，提供几大公司的面试笔试记录-FPGA pen interview questions, several large companies to provide written record of interview
digital-clock-design
- VHDL语言编写的数字时钟设计程序，含源代码和波形仿真，还有顶层电路设计。-The VHDL language of the digital clock design procedures, including source code and the waveform simulation, but also the circuit design.
fm
- 用matlab实现了数字正交解调，叙述了数字正交解调算法的过程与原理-Matlab digital quadrature demodulation, describes the process and principle of digital orthogonal demodulation algorithm
FPGA_USB
- 使用VHDL实现利用USB端口通信的程序，主要完成在FPGA上的通信功能-The use of VHDL implementation procedures for the use of USB port communications, primarily on the completion of the communication function in the FPGA
VHD_Veri_spi
- 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequen
cpldfpga
- cpld 与 fpga的区别 详细的介绍了其主要不同特点-cpld and the difference between fpga
Verilog-SPI
- 用FPGA实现SPI通讯，使用VerilogHDL语言编写，附相对应的MCU端时钟配置注意事项-Using FPGA implements SPI communication, Code use VerilogHDL language, attached corresponding to the MCU side clock configuration Note
Priority_Encoder
- Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded output. Then, it is a multi-input da
Quick51jump
- quick51基本跳线设置表，用于基础quick51开发环境跳线设置-quick51 jump
gpio
- 芯片设计中用于gpio传输接口之间的verilog设计，其中涉及到gpio的传输格式的所有源代码的设计-Chip design for verilog design gpio transmission interface between gpio involving transmission format all source code design
cary_generation
- cary generation code in vhdl