资源列表
Xilinx-ISE9.x-FPGA_CPLD(source).RAR
- Xilinx ISE9.x FPGA_CPLD一书的例程代码-Xilinx ISE9.x FPGA_CPLD a book routines code
FPGA_of_CMI
- 基于FPGA的CMI编码和解码程序，采用VHDL语言设计，通过了仿真验证。-FPGA-based CMI coding and decoding procedures, using VHDL language design, through simulation.
pingball
- 带声音的弹球小游戏,课余设计，使用VHDL-Pinball game with sound
shuzhizhong
- 实现时钟显示,各个模块代码都有，对提高VHDL有帮助-Achieve clock display, each module has a code, help to improve the VHDL
VLSI-Project-Median-filer
- FPGA和ASIC实现的图像中值滤波模块，各模块的仿真结果以及MATLAB,Modelsim联合仿真。这是中科大超大规模集成电路设计优化的final project。附有最终版的report和presention。-FPGA and ASIC implementation of image filtering modules, each module of the simulation results and MATLAB, Modelsim co-simulation. This is the
ARM-Verilog-HDL-IP-CORE
- ARM Verilog HDL IP CORE， ARM IP核，采用verilog编写-ARM Verilog HDL IP CORE, ARM IP core, using verilog write
a_vhdl_can_controller_latest.tar
- CAN 总线的IP核，采用VHDL语言编写。适用各类FPGA-CAN bus IP core, using VHDL language. Apply to the various FPGA
VHDL-DDS
- 基于FPGA的DDS信号源设计，32位相位累加器，产生可调频率-FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency
LED_test
- LED test about the testing of led on fpga
Timing_Constraints_and_Optimization
- SYSNOSYS公司给的关于数字后端时序分析的资料，对于学习数字设计有非常大的帮助，讲得非常全面-SYSNOSYS company gives back timing analysis on digital information, for learning digital design has a very big help, speak very comprehensive
Timing
- 国外关于时序设计的一本非常好的书，写得非常详细，包括时序的分析的原理-Abroad on timing design of a very good book, written in great detail, including the principle of timing analysis, etc.
VHDL-and-Verilog
- verilog和vhdl语言相互转化，有算法和源代码，对学FPGA的同学有帮助-verilog and vhdl language into each other, there are algorithms and source code, help students learn FPGA