资源列表
1123212
- 用VHDL写的一个数字时钟程序，调试成功-Use VHDL to write a digital clock procedures, debugging success
taxi_cnt
- 出租车计费器 根据出租车计费器原理本逻辑模块需包括以下内容：复位模块，开始计费模块，里程计数模块，里程判断模块，停车判断模块，停车计时模块，停车时间计费模块，里程计费模块，总计费模块，LED计时里程计费显示模块，高额费用报警；-taxi count
mouse_vga_2.0
- 基于CycloneIII FPGA开发的PS2鼠标和VGA接口逻辑，采用Verilog编写。-CycloneIII FPGA-based development of the PS2 mouse and VGA interface logic, using Verilog.
LBC_Avalon2.0_SOPC
- 基于SOPC Builder, EP3C40系列FPGA的Avalon总线和MPC8349处理器本地总线LBC，采用Verilog编写的Avalon总线与LBC的转换接口。-Based on SOPC Builder, EP3C40 FPGA family Avalon bus and MPC8349 Processor Local Bus LBC, using Verilog prepared with LBC conversion Avalon bus interface.
VGA
- verilog编写的VGA 2选1切换 经验证，正确-verilog prepared VGA 2-to-1 switching proven correct
divider_with_cache
- 带缓存的除法器,包括test bench，在普通除法器上加上缓存功能-divider with cache
DES
- 该源码采用DES加密标准，采用Verilog编写，时钟为50M，可以扩展为硬件级加密系统-The source uses DES encryption standard, Verilog prepared, the clock is 50M, can be extended to hardware-level encryption system
fwPVerlilog
- 68013与FPGA的通信，包含了固件程序与verilog程序-68013 and FPGA communication, including firmware and verilog program
fir_lowpass
- 简易FIR低通滤波器的verilog代码-Simple FIR low-pass filter verilog code
fenpinji
- 4位10进制数字频率计 可以直接使用-Four decimal digital frequency meter
spi
- spi协议 用verilog 编写 可以在xilinx fpga板子上 ise软件-spi protocol written in verilog in xilinx fpga board ise software
I2C
- iic协议 用verilog hdl语言，可以在xilinx ise软件 编译 综合-iic agreement verilog hdl language can be compiled in xilinx ise software integrated