资源列表
Timingbook
- Timing design for FPGA. Good document for advance learner of FPGA.
yinyue
- 音频播放器 音频播放器可播放三首不同的歌曲，可实现，上一首，下一首，随机播放等功能，需和硬件相连接-Audio player audio player can play three different songs, can be realized, on the one, next, random play functions, and hardware required to connect
Fir_20
- 根据kaiser窗函数实现了Fir滤波器的设计，用于图像处理方面-Achieved under the kaiser window function Fir filter design for image processing ...
mid_filter
- 中值滤波的实现，用于图像的预处理。取出图像噪声-Implementation of median filter for image preprocessing. Remove image noise
selctor
- 二选一的选择输出器....verilog 实现-2 Select an option to achieve the output device .... verilog
decoder2_4
- 这个程序是一个2-4译码器，里面有程序及程序的解释说明，很适合初学者使用-This program is a 2-4 decoder, which has an explanation of procedures and processes, it is suitable for beginners
decoder3_8
- 这是个三八译码器的文件，里面的程序是VERILOG语言编写的，很适合初学者使用-This is a file decoder 38, which the program is written in VERILOG, it is suitable for beginners
decoder38
- 这是个译码器的文件，里面的程序是VERILOG语言编写的，很适合初学者使用-This is a file decoder, which the program is written in VERILOG, it is suitable for beginners
led
- 这是个灯闪烁的文件，里面的程序是VERILOG语言编写的，很适合初学者使用-This is a light flashing file, which the program is written in VERILOG, it is suitable for beginners
ledwater
- 这是个流水灯的文件，里面的程序是VERILOG语言编写的，很适合初学者使用-This is a water lamp documents, which the program is written in VERILOG, it is suitable for beginners
leijiaqi
- 16位流水线加法累加器，用VHDL语言实现，编译仿真通过。-16-bit pipelined adder accumulator, using VHDL language, compiled simulation through.
dengjindu
- 0-100mhz等精度测频，用VHDL实现，编译仿真通过-0-100mhz and other precision frequency measurement, using VHDL implementation, compiled simulation by