资源列表
DataSignal
- 实现并行数据串行传输与接收，最后输出并行数据，中间有偶检验位，有报警位，接收方对接收的数据进行偶校验，无误后接收，有问题则报警。-Parallel serial data transmission and reception, the final output parallel data, the middle even parity bit, alarm bit, the receiver for receiving data even parity, correct reception, t
HEX8
- 描述了七段数码管电路,实现正常的译码功能，并例化为集成8块的数码管模块-Descr iption of seven-segment digital tube circuit, the normal decoding function, and patients into integrated 8 digital control module
SD_Text
- 一个基于nois iiSD-LCM电子相册的IDE IP软核控制程序-Nois iiSD-LCM-based electronic album IDE IP soft core control program
cpu8bit
- 这是一个计算机组成原理综合性实验：设计8位cpu。该cpu是8bit的代码，包含有4个寄存器，一个存储器，还有alu以及控制器。一共可以实现16条指令。-This is a computer composition principle of comprehensive experiment: Design 8 cpu. The cpu is 8bit code contains four registers, a memory, as well as alu and controllers. A
up_down_counter
- the code is written by verilog HDL, and present a kind of up-down counter to realize triangle carrier
clk_div_50
- a kind of frequently used frequency divider as the divider factor is 50 in the code, you can change it as your wish.
Fmeter
- 基于FPGA的VHDL程序，实现双精度频率计功能，包括频率计数、测量占空比等-FPGA-based VHDL procedures to achieve double-precision frequency meter functions, including frequency counting, measuring duty cycle, etc.
VGA_chinese_show
- 利用Verilog语言设计,在VGA上进行汉字显示，效果良好。-Using the Verilog language design, VGA on the character display, with good results.
Reg_16
- 用Verilog语言实现简单的16位状态机-Use Verilog language to design a 16 state machine
coa
- 在Modelsim中实现类MIPS多周期流水化处理器-In Modelsim achieve class multi-cycle pipelined processor MIPS
StopWatch
- 在Modelsim6.3c中编码，与Virtex-II Pro开发板连接实现秒表功能-In Modelsim6.3c encoding, and Virtex-II Pro development board to achieve a stopwatch function
fifo
- 在Modelsim6.3c中实现同步fifo-In Modelsim6.3c achieve synchronous fifo