资源列表
jiaotongdeng
- 用verilog编写的交通控制灯程序，直接就可以运行。对于一般的学者可以参考应用。-Prepared by the traffic control lights verilog program to run directly. Scholars can refer to the general application.
myFPGA
- 流水灯 vhdl程序 十种不同模式的闪烁方式-Vhdl program flow light flashes ten different models
acceleration-for-industrial-robots
- 工业机器人高速速度规划的实现方法的论文，关于梯形和s曲线速度规划的实现方法，IEEE收录，付费下载的，不过估计高校也有买这个数据库。-An efficient acceleration for fast motion of industrial robots
DDS
- FPGA产生DDS，未使用IP核，内含VERILOG程序-FPGA generates DDS, unused IP core, containing VERILOG program
CCD-circuit-of-FPGA-based-design
- 基于FPGA的CCD驱动电路的设计，对CCD驱动新手很有帮助-CCD driving circuit of the FPGA-based design
wp-01044
- FPGA power managment
cf_fp_mul_latest.tar
- CF Floating Point Multiplier
60s-StopWatch--verilog
- stopwatch 60s计数 精确到0.1秒 verilog语言编写-stopwatch verilog
lab15
- 本实验设计了一个微处理器，完全仿真过的！正确无误！Verilog语言编写的！-The experimental design of a microprocessor, complete simulation ever! Correct! Verilog languages!
Soft-core
- 介绍了基于ALTERA 公司FPGA 的双NIOSII 软核处理器在化工设备——脱丁烷塔控制系统中的应用。由于双CPU 处在同一块FPGA 芯片中，并且分担了不同的控制环节，使得整个控制系统与同功能类型产品相比，在成本显著降低的同时，安全性和抗扰动能力大幅提升-ALTERA FPGA-based company introduced a dual-core processor NIOSII soft Chemical Equipment- De-butane tower control syst
FIR
- 基于fpga的FIR滤波器设计,已通过modesim仿真结果正确,verilog编写-Fpga-based FIR filter design, has passed modesim simulation results are correct, verilog prepared
DE2_NET
- 非常好的源代码文件 已经在fpga开发板上验证-Very good source code files have been verified in fpga development board