资源列表
DDFSDemo
- DDFS波形发生器设计，设计软件quartus，有详细注释-DDFS waveform generator design, design software, quartus, with detailed notes
VGA_1
- 电子琴的VGA接哦口，用来显示电子琴的界面，非常美观，可移植性很高的，大家可以参考-Oh flower of the VGA interface port, used to display the keyboard interface, very beautiful, high portability, you can refer to
final_1
- 1. 對於按鍵輸入，請加入聲音輸出電路，分別代表sw1之按鍵回授之音效訊息。每次sw1按鍵壓下時，就送出0.1秒之1KHz聲音。-1. For the key input, please join the voice output circuit, representing the keys sw1 feedback of the audio message. Every time when sw1 button depressed, they sent 0.1 seconds of sound
VHDL
- 先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。-First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is dete
UART
- 简单的uart状态机的编写，作为课程设计的资料，适于入门-UART simple state machine to prepare, as a curriculum design information, suitable for entry-
PIC_project
- PIC 16F84A SOURCE code full 100 working.all modules compiled in one file.-PIC 16F84A SOURCE code full 100 working.all modules compiled in one file.
DDS-Technology
- DDS Technology DDS技术与原理-DDS Technology
dianji
- 电机的FPGA控制，是基于Verilog的。非常简单，传统的三相控制。-FPGA motor control is based on Verilog' s. Very simple, traditional three-phase control.
verilog-uart-rs232
- verilog HDL 描写的uart程序 由PC端接收然后+1返回 等等 东南大学09级4系综合课程设计-verilog HDL descr iption uart program Received by the PC side and then+1 back。 SEU..
xapp223
- UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buffer for Virtex, Virtex-E and Spartan-II FPGAs-UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buf
ece5742010hw9CPU
- 用verilog语言实现CPU， 其中包括几个不同的模块，每个模块中间由总线进行连接-implement the CPU using Verilog language, including the memory, controller,data path, the logic unit.
Digital_Clock1
- 基于Basys2多功能数字钟 verilog HDL 完整工程文件-Based Basys2 multifunction digital clock verilog HDL complete project file