资源列表
8bit-Shift-and-Adder--multiplier
- 8位乘法器，经移位相加算法来实现的，用的VHDL语言-8-bit multiplier, adding the algorithm to realize the shift of
TLC5620c
- 实现对德州仪器厂生产的TLC5620C芯片的测试，产生符合规格的波形，并附上了仿真文件-Achieve TLC5620C Texas Instruments chip factory production testing, resulting waveform to meet the specifications, together with the simulation file
lab5
- VHDL xilinx例子-vhdl xilinx example............
myFPGA
- 流水灯控制，设计出复杂的控制样式和花色，花色在10种以上-The flowing light control design in more than 10 kinds of complex control styles and colors, colors
DEMO_44_ROM
- 这是用vhdl语言描述一个rom的源代码，欢迎大家下载-This is the language used to describe a vhdl source code rom, welcome you to download
Cymometer
- Verilog 编写的频率计，使用8位LED作为显示，Quartus II 6.0的工程文件。保证好用，EPM240T的芯片。使用了66 的资源。-Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used.
SPI
- VHDL语言编写的SPI通信接口,可实现与单片机等外部MCU的通信,且只占用较少的引脚线-Written in VHDL SPI communication interface, can be realized with the microcontroller and other external MCU communication, and only takes less pin line
My_Clock
- 发个我的第一个VHDL代码，秒表。可暂停继续.清0。-My first one made a VHDL code, and a stopwatch. Continue to be suspended. Qing 0.
Lab5_StopWatch_VHDL
- 基于ISE开发环境的212864的秒表驱动程序-failed to translate
dataroad
- VHDL数据通路实验，内容包括：总线通信的基本原则；设备寻址的过程；掌握总线分时复用的方法；掌握多个部件数据通信时数据通路建立过程与控制信号和时序信号的关系。 -VHDL datapath experiments, including: basic principles bus communication Device Addressing process master bus time-multiplexing method grasp the multiple components
DDS_SIN_TRI_BOX
- 利用FPGA实现DDS，可输出正弦波，输出频率可调.-FPGA implementation using DDS, sine wave output, the output frequency is adjustable.
daout-Sine-wave
- 正弦波的vhdl输出，使用VHDL编写的，已经通过调试-Sine wave output of the VHDL, the use of VHDL prepared already through debugging