资源列表
adder
- adder in vhdl , ff , using xilinx ise -adder in vhdl , ff , using xilinx ise
shuziluji
- 纯VHDL文件 拥有闹铃 整点报时 日历 使用方法（打开文件shizhong.gdf文件编译即可（本人使用maxplus-Pure VHDL files have calendar alarm whole hour to use (you can open the file shizhong.gdf file compilation (I use maxplus))
VGA
- 嵌入式FPGA初学者源代码，VGA显示器驱动显示程序，调试良好，下载即可运行，自我分析学习的源代码典范-Embedded FPGA source code for beginners, VGA display driver display program, debug good download to run, self-analysis model for studying the source code
VerilogHDL
- 很多verilog编写实例，简单易行，很适合初学者-Verilog written many instances, simple, very suitable for beginners
NCVerilog_tutorial-chinese
- linux下cadence nc_verilog工具使用教程，中文的，很详细，很适合学习-tool under linux cadence nc_verilog tutorials, Chinese, very detailed, very suitable for learning
rtl
- 基于S10新品的2x2矩阵乘模块，附带双精度的乘法，除法ip核(2x2 matrix multiplication module based on S10 new product, with double precision multiplication, division IP kernel)
vh
- 有用的VHDL源代码-useful VHDL source code
eeprom-model
- 基于fpga的eeprom设计，适合用于eeprom的仿真-eeprom model based on FPGA
VHDL
- 1、根据设计要求，完成对序列信号检测器的设计。 2、进一步加强对QuartusⅡ的应用和对VHDL语言的使用。-1, according to design requirements, to complete the sequence of the signal detector design. 2, to further strengthen the Quartus Ⅱ applications and the use of the VHDL language.
communicate-with-the-computer
- 用Altera Quartus II 的VHDL语言完成的串口与电脑通讯的源代码-The use of Altera Quartus II VHDL language to complete the serial port to communicate with the computer source code
queues
- queue hardware deisgn with verilog
clockdiv_teste
- Clock division program write in Verilog with selected divider (32 bits)