资源列表
Music_HLD3Core(400)_(C)
- 这是非常好的vhdl例子，大家看看吧，希望与大家分享更多的好东西-It is a very good vhdl example, we look at it, and we hope to share more good things
Verilog
- 里面有一些FPGA设计的常用模块，已经做好 立刻调用即可 -There are some common FPGA design module, ready to immediately call
DS18B20_ok
- DS18B20转UART输出，每个温度点两个字节-DS18B20 to UART output，Two bytes each temperature
traffic
- 用VHDL交通灯的实现,主干道红绿黄分别为40S20S5S，次干道红绿黄分别为20S5S，采用状态转换-Implementation of traffic lights with VHDL, red, green and yellow were the main road 40S20S5S, red, green and yellow secondary roads were 20S5S, using state transition
RISCMCU
- riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
FPGA_car_drive
- 基于EasyFPGA030的模拟乒乓比赛设计.-Simulation-based ping-pong game EasyFPGA030 design.
verilogHDL
- verilog HDL 的课件，东南大学的课件，具有学习价值-verilog HDL courseware, Southeast University, courseware, a learning value
light_state_machine
- 用Verilog HDL语言写一个雷鸟车灯控制器。汽车工作状态有：空闲，左转弯，右转弯，告警。-Verilog HDL language used to write a Thunderbird lights controller. Working state vehicle are: idle, turn left, turn right, alarm.
14_tlc549adc
- 利用状态机实现对TLC549的采样控制，实验时可调节电位器RW1（在开发板底板左下角），改变ADC 的模拟量输入值，数据采集读取后在数码管上显示。可以自己用万用表测一下输入电压， 然后与读取到的数据比较一下。注意：数码管显示的数据不是最终结果，还需要转换。-Using the state machine to achieve the TLC549 sampling control, experiment adjustable potentiometer RW1 (development
FIR_filter_design
- FTR滤波器设计文档，几个常用方法，切比雪夫，流水线，FFT-FTR filter design documents, several commonly used methods, Chebyshev, pipeline, FFT, etc.
fix_float
- 该程序的功能是将18位的定点数转换成15位（1，5，9）格式的浮点数，-The program' s function is to set the 18-bit conversion of 15 points (1,5,9) format floating-point,
Ctl_LCD
- FPGA控制LCD代码,实测可用,仅供参考,如需转载请说明-FPGA control LCD code, measurement can be used for reference purposes only and for reprint please indicate