资源列表
USBInterfacewithFPGA
- 基于USB接口并用FPGA控制的系统，实现实施的数据传输和调试-USB Interface with FPGA based control system to realize the implementation of data transfer and debugging
FPGA
- 基于FPGA哥专用芯片双核心处理，MB86S02 CMOS 视频采集实现嵌入式视频采集与处理的设计过程-FPGA-based ASIC dual-core processing Colombia, MB86S02 CMOS video capture video capture and processing of embedded design process
vga_disp
- 本程序为自己毕业设计用，可通过数据控制VGA显示动态竖彩条，为了使大家容易理解此程序，我对其中关键处作了详细说明，希望对FPGA爱好者和FPGA初学者有用!-The graduate program designed for their own use, data control via dynamic vertical color VGA display section, in order for you easy to understand this process, key Departm
I2C
- I2C总线接口的Verilog源码文件和modelsimd的测试文件-Verilog source code of I2C bus interface and testbench code of modelsim.
xiangweileijiaqi
- 相位累加器，是数字频率合成器的重要组成部分。这是verilog代码。-Phase accumulator, digital frequency synthesizer is an important part. This is the verilog code.
digital-frequency
- 数字频率计 采用Verilog语言编写，分为8个模块，分别是计数器，门控，分频，寄存器，多路选择，动态位选择，BCD译码模块-Digital frequency meter using Verilog language, divided into eight modules, namely, the counter, gated, frequency, register, multiplexer, Dynamic Choice, BCD decoding module
8adder
- 本实验示例中的8 位二进制并行加法器即是由两个4 位二进制并行加法器级联而成 的图13-4 所示的逻辑电路是由两个并行进位4 位加法器级联而成的8 位二进制加法 器-This is simple adder of 8 by VHDL.
leapyear
- 在Xilinx ISE软件下关于瑞年计数器的工程，可以判断某一年份是否为瑞年。包含代码及测试代码，已经通过编译，综合，仿真波形完全正确。-Under the Xilinx ISE software counters on the Swiss-year project, can determine whether a given year in Switzerland. Contains code and test code, has passed compiled, integrated, si
prathap
- a difficult technique compact programs in verilog-a difficult technique compact programs in verilog..
DE2_70_CAMERA_v1.0.2
- 應用程式verilog相關事件，參考文件-Verilog application related events, refer to documents ... etc.
async_uart
- 用verilog写的串口接收发送通信程序，已经在cyclone EP1C12Q240C8调试通过-Serial receiver with verilog send written communication procedures, has been adopted in the cyclone EP1C12Q240C8 debugging
VerilogFPGAUSB
- 用Verilog（FPGA）实现USB源代码大家-Using Verilog (FPGA) source code we look to achieve USB