资源列表
lcddispay
- 这个文件是ISE文件，里面描述了一个四位数码管的动态显示程序-This file is the ISE file, which describes a four digital control of dynamic display program
1
- 实现按键中断，在NIOS II IDE平台上实现按键中断，按键驱动程序在Quartus ii里面用VHDL编写。-interrupt
Quartus2(FPGACPLD)
- 在Quartus2上的FPGACPLD设计，PDF文档-The FPGACPLD design in Quartus2 , PDF documents
HDB3
- 采用FPGA产生数字基带系统传输码型HDB3码，采用《通信原理》例子设计。-Generated by FPGA digital baseband transmission code HDB3 code system, a " communication theory" example design.
trafficlamp
- 基于FPGA的交通灯设计，有红绿黄三色，与实际完全相符，采用三进程设计！-FPGA-based design of traffic lights, with red, green and yellow three-color, fully consistent with the actual, using the three process design!
shift_reg
- 移位寄存器，Verilog实现，有实验说明文档。-Shift register, Verilog implementation, there is experimental documentation.
my_xor
- 异或门，Verilog实现，包含实验说明文档。-XOR gate, Verilog implementation, including test documentation.
my_xnor
- 同或门，Verilog实现，配有实验说明文档。-With or door, Verilog implementation, with experimental documentation.
my_reg
- D触发器，Verilog实现，配有实验说明文档。-D flip-flop, Verilog implementation, with experimental documentation.
rs_dec_enc_latest.tar
- Reed-Solomon (255,251). in VHDL.
reed_solomon_decoder_latest.tar
- reed solomon (204,188). in verilog.
sin_generator
- Sin Generator. 16 points on period.