CDN加速镜像 | 设为首页 | 加入收藏夹
当前位置: 首页 源码下载 嵌入式/单片机编程 VHDL编程

资源列表

« 1 2 ... .32 .33 .34 .35 .36 3037.38 .39 .40 .41 .42 ... 4323 »
  1. XC3S700_LCD_Test

    0下载:
  2. 红色飓风3S700AN开发板LCD测试例程-Red Hurricane 3S700AN ​ ​ LCD development board test code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:711.45kb
    • 提供者:Eddie
  1. XC3S700_AUDIO

    0下载:
  2. 红色飓风3S700AN开发板音频编解码测试例程-Red Hurricane 3S700AN ​ ​ development board audio codec test code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-10
    • 文件大小:2.27mb
    • 提供者:Eddie
  1. XC3S700_PS2_Test

    0下载:
  2. 红色飓风3S700AN开发板PS2接口测试例程-Red Hurricane 3S700AN ​ ​ PS2 interface development board test code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-06
    • 文件大小:1.44mb
    • 提供者:Eddie
  1. XC3S700_7SEG_Test

    0下载:
  2. 红色飓风3S700AN开发板LED数码管测试例程-Red Hurricane 3S700AN ​ ​ development board seg LED test code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:527.99kb
    • 提供者:Eddie
  1. pn_combine

    0下载:
  2. pn码生成以及误码率检测程序,开发环境为Altera-pn code generation and BER testing procedures, development environment for Altera
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-09
    • 文件大小:14.7mb
    • 提供者:Shawn Chen
  1. DE2_SD_Card_Audio

    0下载:
  2. DE2_SD_Card_Audio程序,有简单的播放,快进,快退,随即循环顺序播放-DE2_SD_Card_Audio procedures, a simple play, fast forward, rewind, then loop order of play
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-09
    • 文件大小:15.6mb
    • 提供者:张皮有
  1. qjq

    0下载:
  2. 通过ISE软件采用VHDL语言实现1位全加器的功能-Through the ISE software using VHDL language a full adder function
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:2.91kb
    • 提供者:卢晓伟
  1. D_FF_ok_D

    0下载:
  2. Learning FPGA students can see, this code USES VHDL language to write D flip-flop, not only can learn QUARTUS software, also can better enhance the digital circuit design.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:102.1kb
    • 提供者:朱家林
  1. full_add4_ok_

    0下载:
  2. Learning FPGA students can see, this code USES VHDL language to write four full adder, not only can learn QUARTUS software, also can better enhance the digital circuit design.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:137.07kb
    • 提供者:朱家林
  1. pwm_ok_PWM

    0下载:
  2. Learning FPGA students can see, this code written by PWM generator using VHDL language, not only can learn QUARTUS software, also can better enhance the digital circuit design.
  3. 所属分类:VHDL编程

    • 发布日期:2017-04-07
    • 文件大小:166.37kb
    • 提供者:朱家林
  1. odd_div_ok_

    0下载:
  2. Learning FPGA students can see, this code USES the VHDL language written by an odd number of frequency divider, not only can learn QUARTUS software, also can better enhance the digital circuit design.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:643.53kb
    • 提供者:朱家林
  1. seq_sig_generator_ok_

    0下载:
  2. Learning FPGA students can see, this code is written using VHDL language sequence generator, not only can learn QUARTUS software, also can better enhance the digital circuit design.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2016-01-26
    • 文件大小:124kb
    • 提供者:朱家林
« 1 2 ... .32 .33 .34 .35 .36 3037.38 .39 .40 .41 .42 ... 4323 »
搜珍网 www.dssz.com