资源列表
YIWEIJICUNQI
- 两种移位寄存器的设计，分别为通用移位寄存器跟桶形移位寄存器-Two kinds of shift register design, namely, universal shift register with the barrel shifter
CHUANKOU
- 通过对时钟分频，串口接收和发送以及串口调试程序的编写实现数据的接受和发送-Through the clock divider, and a serial port receive and transmit serial debugging procedures for the preparation of the receiving and sending data
shixuzhuangtaiji
- 通过verilog hdl语言实现对时序状态机的编写-By verilog hdl language for writing timing state machine
JIFENLBOQI
- 通过verilog hdl语言完成对积分梳妆滤波器的设计-By verilog hdl language used to complete the design of the integrator comb filter
RS
- 通过verilog hdl语言实现RS编码器与译码器的设计-Verilog hdl language through the RS encoder and decoder design
chengfaqi
- 通过verilog hdl语言实现伽罗华域GF（q）乘法器设计-By verilog hdl language Galois field GF (q) Multiplier
SUANSHUJISUAN
- 通过verilog hdl实现加法器乘法器，除法器的设计-Achieved through verilog hdl adder multiplier, divider design
data
- 通过verilog hdl实现对数据的比较，分配器选择-Verilog hdl achieved through the comparison of the data, the distributor selection
Digital-clock
- 数字时钟6位数码管显示。主要器件为74ls48和74ls160 /74ls161。功能：1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能-Digital clock six digital tube display. Main components of 74ls48 and 74ls160/74ls161. Features: 1. Shows hours, minutes, seconds. (2) a 24-hour or 12-hour clock. 3 a sc
SiDianDingWei
- 用FPGA控制、Verilog HDL语言编写、实现在已知四点的情况下测量任意一点的功能-Using FPGA control, Verilog HDL language and realized in the case of the known four-point measurement function at any point
clock_gating
- 在FPGA里运用Verilog HDL编写实现门控时钟，而不产生毛刺-In the FPGA using Verilog HDL prepared to achieve clock gating, without glitches
demo
- NiosII的C代码,包括网卡,lcd,usb,串口,按键.-NiosII C code, including network cards, lcd, usb, serial, key.