资源列表
caitiao
- QuartusII软件写的四条竖彩条信号，通过ADV7171芯片转成模拟信号在监视屏上显示。-The color bar signal which are writen by VHDL ，with the data of the signal converted to analog signal by ADV7171 ，are showed on TV monitor .
blank
- 监控摄像头传入数据，通过芯片TVP5150转换成数字信号，其中sav_check.vhd检测帧头，converter.vhd将信号转换成Y，Cb，Cr格式，最后write_blank.vhd重新组建完整数字信号，最后通过ADV7171转成模拟信号输出到监视器上。这中间，可以对Y做各种图像处理，如滤波处理，均衡处理，只需要在converter之后添加处理文件即可。-Surveillance camera incoming data through the chip TVP5150 converte
behaviour_lot
- lot of program in the behaviour model using vhdl languag that will help for othres
uart16750_latest.tar
- UART Module VHDL CODE TESTED ON FPGA
fsk
- 使用quartus13.0 搭建的FSK调制解调仿真系统使用了DDS技术和正交相关解调。-Quartus13.0 built using FSK modulation and demodulation simulation system uses DDS technology and quadrature coherent demodulation.
pulse_gen
- Pulse generator using VHDL for most of FPGAs
waveform
- The waveform of pulse generator code
control
- The Pipeline SPIN model using VHDL
decode
- The pipeline SPIN VHDL code (decode part)
execute
- The pipeline SPIN VHDL code (execute part)
TimeClock
- 能够在max3上显示24小时，并且具有定时功能，能够设定闹钟，具有正点报时-Max3 can display 24 hours, and has a timer function, be able to set the alarm, with punctual timekeeping
fetch
- The pipeline SPIN VHDL code (fetch part)