资源列表
jianyiluojifenxiyi
- 基于verilog 的简易逻辑分析仪，已经过调试-Simple verilog based logic analyzer, has been testing
sanjiaobo
- DDS信号源中关于三角波的设计，程序上采用VHDL编写，结果仿真通过-DDS signal source on the triangle wave design, procedural preparation of VHDL simulation results through
sin
- DDS信号源设计中关于正弦信号的波形发生器，采用VHDL编写完-DDS signal source design on the sinusoidal signal waveform generator, using VHDL prepared END
Xilinx_Spartan3E_VGA_PS2
- 使用Spartan3E 开发板实现VGA显示和PS2键盘接口，完成了简单的文字处理功能和图片显示功能。-Use Spartan3E development board to achieve VGA display and PS2 keyboard interface, complete a simple word processing features and picture display.
dian_ji
- 电机驱动源代码，采用VHDL描述，已在开发板上实现，肯定没问题的。-Motor-driven source code, using VHDL descr iption has been achieved in the development board, and certainly no problem.
liangzhu
- 采用verilog hdl设计的音乐播放器，梁祝，在红色飓风2上测试通过。-Using verilog hdl designed music player, Butterfly in Red Hurricane 2 on the test.
at8253a
- 采用VHDL语言设计的8253控制器，实现定时和计数等功能，仿真通过。-Design using VHDL 8253 controller, timing and counting functions, through simulation.
freq_div2
- 采用VHDL语言设计的分频器，仿真和实际电路板都测试过，没问题。-Divider using VHDL design, simulation and actual circuit boards are tested, no problem.
minute_ct
- 采用VHDL语言设计的分钟计时器，是时钟设计的一部分，已仿真和测试通过。-Design using VHDL-minute timer, the clock part of the design, simulation and testing has been passed.
fifo1k_32
- vhdljichu,完成vhdl中对sdram控制器的功能-vhdljichu, completed in vhdl sdram controller functions for
control_interface
- vhdl中的pci接口控制部分，完成pci接口读写-vhdl pci interface control section in
plx_r
- vhdl中的频率锁相环部分，完成时钟配置-part of the frequency locked loop vhdl complete clock configuration