资源列表
jiaotongdeng
- 交通灯，模拟显示十字路口两个方向的交通通行情况。两个方向均用红、黄、绿灯指示实际状态。用LED同时显示两个方向状态的时间。时间计数方式为倒计数方式。技术参数为绿(红)50秒、黄(红)5秒、红(绿)30秒和红(黄)5秒。-Traffic lights, crossroads analog display case crossings in both directions. In both directions with red, yellow and green indicate the actu
JIAFA_4
- 加法器，采用流水线技术设计四级加法器，VHDL实验-Adder, four pipelined adder technical design, VHDL test
LED
- xilinx V6板卡上的根据时钟的LED流水灯程序，包括chipscope的时序提取模块，已在在V6上验证通过-xilinx V6 under the clock on the board LED light water procedures, including the timing chipscope extraction module has been verified through on the V6
tv_tft320x240_red2-35
- 本实验是红色飓风上的sdram的应用实例，希望有用-This experiment is red hurricane sdram on application examples, useful
fpga_dds
- 设计一个直接数字频率合成(DDS，Direct Digital Synthesis)，DDS是一种新型的频率合成技术。DDS 技术是一种把一系列数字形式的信号通过DAC 转换成模拟信号的合成技术。-Design a direct digital frequency synthesis (DDS, Direct Digital Synthesis), DDS is a kind of new type of frequency synthesis technologies. DDS technol
Multiplier-code-with-testbench
- VHDL code for synthesizable Multiplier with testbench
display
- seven segment display apllication with only one push button up counter
flash
- fpga nios ii vhdl qsys
filter_lpm_shaping
- 4倍内插值的fir成型滤波器，语言vhdl，工程已建立，可以直接运行-4x interpolation of fir shaping filter, language vhdl, project has been established, you can directly run
uart
- 一个实用的uart协议模块，使用verilog 实现-A practical uart protocol modules, use verilog to achieve
myuart
- 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and
cordic
- cordic一次移位，需要多次的话可以通过多次条用-codic algorithm unit