资源列表
syn_fifo
- 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
logic_new3
- verilog简易逻辑分析仪2003年全国大学生电子设计大赛，仪器仪表题-verilog logic
Spartan-3E
- Spartan+3E中文用户指南, Spartan+3E英文手册人工翻译过来的pdf版本-Spartan+3E Chinese user' s guide, Spartan+3E English translation of the manual labor pdf version
uartverilog
- 用verilog编写的FPGA 串口通信程序，开发平台quartus 11.0 经过测试，可以使用-verilog serial communication procedures, the development platform quartus 11.0
clockend
- 基于QuartusII开发环境，Cyclone III开发板的VerilogHDL多功能数字钟程序。可实现24小时计时，手动校时，闹钟，整点报时功能。分频模块在仿真和烧写是需要改变。-QuartusII based development environment, Cyclone III development board VerilogHDL multifunction digital clock procedures. Can achieve 24-hour clock, manual ti
temperature
- DS 18B20的VerilogHDL驱动程序-DS 18B20 driver' s VerilogHDL
Experiment09
- verilog语言编写的FPGA驱动VGA的程序，经过测试-FPGA using verilog language VGA driver program, using the development platform for quartus 11.0
spi-dac-with-spartan-3e-fpga
- DAC details has been given for FPGA
CODING
- VHDL CODE FOR LDPC CODES
VGASWITCHPICTURE
- Verilog语言编写，VGA显示图片自动切换程序。图片显示为哆啦a梦的多幅图片切换。通过字符显示图像。-Verilog language, VGA display picture automatically switching program. Pictures appear as a dream duo toggle multiple images. Through the character display images.
SIN
- 使用rom生成sin曲线，VHDL实验课上做的实验，适合初学者。-Sin curve generated using the rom, VHDL experimental class to do the experiment, suitable for beginners.
qiangdaqi
- 四人抢答器， 有4组抢答，系统开始后进入抢答状态，抢答开始后20秒倒计时，20秒倒计时后无人抢答显示超时，发出报警信号；当有一路抢答按键按下，该路抢答信号将其余各路抢答信号封锁，同时铃声响起，显示该路抢答台号；一轮结束后按复位键将所有状态复位。-Four Responder, Responder has four groups, the system begins to enter the answer in the state, began to answer in 20 seconds af