资源列表
TLC549
- tlc549AD芯片的采样程序，但是基于AD芯片的采样率的限制，最大也就50khz左右-Tlc549AD chip sampling procedure, but the limitation of sampling rate based on the AD chip, the biggest is about 50 KHZ
a
- 用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写-verilog ise divider
Q
- 求模程序。。没有调用ip核，根据数学算法，逼近的思想，来编写的求模程序-verilog square
CLOCK
- 数字时钟的实现，能够显示时间，包括时，分，秒的信息。-The realization of the digital clock that can display time, including hours, minutes and seconds of information.
lab4_5
- 用VHDL实现串行除法器，16位被除数，8位除数-Using VHDL serial divider, 16 dividend, divisor 8
lab4_4
- 用VHDL实现16进制到10进制以及10进制到16进制的转换-Using VHDL 16 to 229 10 to 16 hex and 10 hex hex conversion
ds18b20_20130712
- 基于XILINX VERTEX-5的ds18b20温度传感器的状态机控制，使用状态机对一线传感器进行控制，用示波器进行观察。-The design is based on the xilinx vertex-5 aimed to realizing the goal of detecting the temperature through ds18b20.
Lab2_Part1
- display BCD code(0-9) using 7-segment displays in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
Lab2_Part2
- converts a 4-bit binary code to 2-digital BCD code in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
part1
- a 4-bit synchronous counter using T-Flip Flops and AND gates in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
436394195AlteraFPGA
- FPGA开发板原理图，飓风二代FPGA学习板电路图、封装库-FPGA development board schematics, Hurricane II FPGA board Schematic Library
integrative-concept
- 本书是有关verilog语言整合的概念，是verilog语言梳理条理的精华所在，推荐一读。-This book is about the concept of integration verilog language, verilog language is the essence of organized combing is recommended reading.