资源列表
memory
- The pipeline SPIN VHDL code (memory part)
clock
- verilog hdl 编写的八位数码管24进制的数字钟，含清零功能-verilog hdl written eight digital tube 24 hex digital clock, with clear function ...
acquisition_ad9887a1.3
- FPGA 将ad9887a输出的数据写入FIFO_00中，并计数输入的点频，行频和当前行频。将计数的点频，行频和场频数，以及行场信号输出信号（高电平有效）。 点频计数值为前一行的数据量。行频计数输出是前一场的计数。当前行频计数输出是当前行在这一场的行数。-FPGA will ad9887a output data is written FIFO_00 in and point counting input frequency, line frequency, and current line
zhengxianbo
- 正弦波发生器，基于verilog语言编写的，不用用DAC模块，直接输出0和1电频，经过RC滤波后就可得到波形-Sine wave generator, based on verilog language, do not use the DAC module, direct output power frequency 0 and 1, RC-filtered waveform obtained after
delta-sigma-DAC
- 根据FPGA的∑-Δ D/A转换器的设计与实现策略，∑-Δ DAC的内部仅由2个10位的二进制加法器，1个10位的锁存器和一个D触发器组成，用FPGA实现时只需耗费极少的逻辑资源，即使用最小的FPGA也能实现。这是∑-Δ DAC实现的verilog语言-According to the FPGA Σ-Δ D/A converter design and implementation strategies, Σ-Δ DAC' s internal only by the two 10-bit
multi-CPU
- Verilog开发的能下载到FPGA实验板上运行的多周期CPU-Verilog can be downloaded to the FPGA development board running experiments multi-cycle CPU
vertex5_digilent_emac0_1gbps
- Digilent公司开发板GENESYS板载1Gbps网口实现驱动程序，实现回环模式的发送。-Digilent development board GENESYS onboard 1Gbps ethernet driver, send the loopback mode
SERDES_Introduction
- SERDES & CDR Fundamental SERDES Measurements How to Evaluate a SERDES Device? High Speed Design Consideration
EDApinlvji
- EDA频率计程序 EDA频率计程序-Frequency meter program EDA EDA EDA frequency meter frequency meter program procedures
KEY_PWM
- fpga产生可调的PWM波形,通过按键去控制其占空比-adjustable PWM waveform generated by fpga , through the buttons to control its duty cycle
vendingmachine
- 描述了一个简单的自动售货机模型，并附带Testbanch对各种情况进行了仿真。-Describes a simple model of a vending machine, and comes Testbanch variety of situations were simulated.
4x4-Keypad
- fpga的一个小程序用于3s500e 4*4键盘模块-fpga is a small program used 3s500e 4* 4 keyboard module