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资源列表
8jiafaqi
- 利用此程序可以实现8位超前进位加法器的功能-This program can be used 8-bit look-ahead adder function
clock
- 数字钟 用VHDL 编写，内含QUARTUSII软件-digital clock
DE2_LCM_CCD
- DE2开发板上用DC2模块和LCM模块实现的数字照相机源代码-DE2 development board with the module and the LCM module DC2 Digital Camera Source
mWdB
- 毫瓦和对数转换算法，这个算法以及申请专利。本实施列可以给大家共享-mWToDb
DE2_TV
- 友晶公司DE2开发板的TV示例完整源代码 FPGA Cyclone-Friends of the crystal of TV company DE2 development board complete source code for FPGA CycloneII sample
vgaChars
- 有关vhdl的硬件实现VGA设计的代码。 -This is a tutorial on how to create proper 640x480 vga output using the altera UP2 development board.
watchver_cr2
- Stopwatch example -Stopwatch example !!!!!
testbench
- altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。-altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.
keyscan_test
- 针对机械式按键存在的抖动问题，用verilog HDL编写了一个采用防抖方案并对按键次数计数的模块，已经在ISE综合通过！-Keys exist for mechanical jitter, with verilog HDL prepared a program with anti-shake button and count the number of modules have been integrated by ISE!
93317478verilog.HDL.examples
- hdl代码的相关应用，里面还附有相关实例和介绍说明 -hdl code related applications, which also introduced with examples and instructions related
eda2
- 一个带记数使能，同步复位，带进位输出的增一 六位二进制记数器，记数结果由共阴极七段数码管显示-One with a count enable, synchronous reset, into digital output by 16 binary counter, counting the results from the common cathode seven-segment LED display
EDA3
- 该程序是一个带记数使能，异步复位，带进位输出的增一 二十进制记数器，记数结果由共阴极七段数码管显示-The program is a band count enable, asynchronous reset, into digital output by 12 decimal counter, counting the results from the common cathode seven-segment LED display