资源列表
AnalizatorAndCounter
- VHDL counter project fo Altera DE2 Development Board-VHDL counter project fo Altera DE2 Development Board
time_clock
- 时钟数码管显示FPGA例子-Verilog语言-Clock digital display FPGA example-Verilog language
8085
- 8085 vhdl source code in vhdl
wallacetree8mult5asynch
- this file is vhdl code for 8*5 wallacetree multiplier.
DEMO22
- ＶＨＤＬ源程序，ＭＡＸＰＬＵＳ 环境下运行，电梯控制系统-VHDL source code, under Operation Converter, elevator control system
DigitClock
- 基于FPGA的电子钟设计，有时分秒的按钮调节。重置，清零功能-FPGA-based electronic clock design, sometimes the buttons to adjust the minutes and seconds. Reset, clear function
NIosII
- NIosII软处理器快速入门,内容挺详细的，至少对我这种初学者而言-Quick Start NIosII soft processor, the contents of very detailed, at least for beginners in terms of my
spi
- fpga 作为丛机 8位 spi信息传输 。。。。。。(FPGA 8 bit SPI information transfer as a cluster machine......)
stopwatch1
- 用vhdl实现的数字秒表，显示四位值，最大计时时间为99.99s，全部通过验证，并且在FPGA上得到很多的结果-Using vhdl implementation of the digital stopwatch display four values, the maximum time time 99.99s, all validated, and get a lot of the FPGA results
55593396NIosII
- altera nios相关数据手册,对研究NIOS的人员很有帮助-altera nios data manual for the study of NIOS staff very helpful
exp_ps2_led
- 通过编写程序实现键盘的功能，可以调用键盘上的任意键实现输入与相应的输出-Achieved by programming the keyboard functions, you can call any key on the keyboard corresponding to the input and output
ex2
- 七段码 练习使用 verilog 源代码-Seven-segment code practice using verilog source code