资源列表
distributed_ram
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
triple_sdi_rx
- XILINX VIRTEX5 triple_SDI接受端-XILINX VIRTEX5 triple_SDI receiving end
I2C
- 24c02的学习，简单的I2C程序，读写E2PROM将数值送到P1，LED等显示。-24c02 study, a simple I2C procedures, read and write values to the E2PROM to P1, LED and other displays.
jtag
- jtag技术规范，以及标准的并口jtag下载电缆的资料
i2c_master
- I2C Controller for Serial EEPROMs
Lab01
- verilog 入门练习，包括完整的Verilog实例，包括仿真的所有文件，主要是关于寄存器定义、名称映射、RS触发器定义等内容-verilog Getting exercises, including full Verilog examples, including all documents simulation, mainly on the register definition, name mapping, RS trigger definition, etc.
DigitalClock
- VHDL的数字时钟程序 24小时计数显示； 具有校时功能（时，分） ； 实现闹钟功能（定时，闹响）；-VHDL digital clock counting procedures showed that 24 hours with a school function (hours, minutes) the realization of an alarm clock function (timing, downtown ring)
ProgramText
- we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.-we will use the cables Spartan3 FPGA design to a specified counter using the VHDL language.
mux4_1
- Verilog Code for 4*1 Multiplexer with testbench file-Verilog Code for 4*1 Multiplexer with testbench file...
PAL
- PAL_D电视信号VHDL以及verilog源程序！ FPGA设计PAL_D电视信号！VHDL源程序！两个程序都是黑白的video信号，输出可以直接在视频显示器上显示。 -PAL_D TV signal VHDL and Verilog source!
20084142011081129
- VHDL设计举例：直流电机控制器.docgfddrhd-VHDL design, for example: DC motor controller. Docgfddrhd
61i_cic_v3_0_vhdl_ise
- CIC code In VHDL+Xlinx ISE