资源列表
PseudoHC11_MCU
- This extensive proyect turns an FPGA or CPLD into an HC11 simulation. It takes in various opcodes and performs several 8bit operations. The package includes an ALU, UART, RAM module, LCD display and 7 segments as well.-This extensive proyect turns an
quartus
- 基于FPGA的波形发生器的源代码啊quatusII的干活-Working source code for the FPGA-based waveform generator ah quatusII the
Example-b8-3
- 学习使用DO文件进行仿真的基本方法,根据ModelSim提供的命令或者Tcl/Tk语言的语法，将仿真Cmd流程的仿真命令依次编写到扩展名为“do”的宏文件中，然后直接执行这个DO文件，就可以完成整个仿真流程-DO learn how to use basic file simulation method, according to the syntax of the command or ModelSim provides Tcl/Tk language will flow simulation
code-water-no-cache
- 5级流水无cache的cpu代码，基于verilog，串行，两级流水-cpu code with no water nor cache
aa
- 洗衣机控制vhdl，洗涤、漂洗和脱水，每个功能持续的时间分别为20秒、15秒和10秒-vhdl
adma.tar
- 基于AMBA规范的总线VERILOG HDL 源代码
quick_fft_1024_8
- 快速傅里叶变换FFT，绝对经典，速度极快，仅仅只有12us，市面上绝无仅有，自己写的，无私奉献出来，希望大家好好利用，好好学习-Fast forious transform,very very very quickly,only 12us,download,no doubt
sericommu
- 串口通信程序.在波特率为9600的串口通信程序-serial communication program. The baud rate for the 9600 serial communication program
full_adder
- this vhdl code implement 1 bit full adder logic algorithm-this is vhdl code implement 1 bit full adder logic algorithm
TCD1251
- 应用verilog语言，对TCD1251元器件进行驱动，以实现相应功能-To drive TCD1251 device
mux2
- this is multiplexer gate in vhdl run under active hdl
failed-to-translate
- 4x4矩阵键盘实验Cfailed to translate-failed to translate