资源列表
键盘实验文件_modify
- 键盘数据读取，并显示在数码管上，速度可达到100M频率(Read the keyboard data, and display on the digital tube, frequency speed can reach 100M)
SPI-Master-master
- Use code for Maser SPI
CPU_Verilog
- 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
xjrsb
- Based on matlab GUI interface design, Complete class-based image processing, contains all of the source code, auto image, Related impulse response analysis algorithm and inspection.
ndbwu
- Including scr ipt files and function files in the form, Clustering analysis based on Euclidean distance, Waveform data analysis.
megan_fox
- kszzwezrgf wdgasgd wuegfgsgf wuwugdsd
RX_IP_Source
- 串口接收ip核，配合 nios 使用，减少cpu资源开支。(uart receive TX_IP_Source)
Coding Files
- Through this paper our attempt is to give a onetime networking solution by the means of merging the VLSI field with the networking field as now a days the router is the key player in networking domain so the focus remains on that itself to get a good
sdr_sdram
- sdram使用接口仿真，altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method)
traffic_light
- 使用Verilog编写交通灯控制代码，能够直接进行运行仿真。(Using Verilog to write traffic light control code, can run the simulation directly.)
timing_constraints
- 方法能够自动地约束 PLL 的输入和输出时钟。ALTPLL megafunction 中指定的所有 PLL 参数都用于约束 PLL 的输入和输出时钟。(Methods can automatically constrain PLL input and output clock.Named in ALTPLL megafunction.All PLL parameters are used to constrain PLL input and output clocks.)
可逆计数器VHDL描述
- 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4，利用Xilinx ISE软件，利用VHDL软件编写可逆计数器，包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, written in a reversible