资源列表
Verilog_UART
- universal asynchronous (UART) are designed in averilog module to easly implemented.-universal asynchronous (UART) are designed in averilog module to easly implemented.
Ring_mem_VHDL
- 响铃和内存管理功能的VHDL语言，用于程控交换机中的Xillinx芯片与DSP和ADDA等芯片配合实现交换机的功能-Ringing and memory management features VHDL language, for program-controlled switchboards in Xillinx and ADDA chip and DSP chip, etc. with the function of switches realize
xlgeneratebutton_example
- its a xlgenerator ie xilinx and matlab for cordic
sdr
- SDR控制器的设计和仿真testbench-the controller of SDR memory,and the simulation of testbench
FPGA
- 应用于FPGA开发中QaurtusII出现 的警告和错误说明-The errors && warning for QaurtusII
src
- 8254 fpga vhdl语言实现代码-8254 fpga vhdl language code
xinhaofashengqi
- 信号发生器代码能实现正弦波方波锯齿波等波形-The program can realize sine wave of square wave sawtooth wave waveform
LCD12864
- VHDL编写的LCD12864控制程序，是开发板上带的，绝对正确。本人验证过。希望对学习这方面的朋友有用。-VHDL LCD12864 control procedures, the development board with the absolute right. I have verified. I hope to learn this aspect of the useful friends.
miaobiao
- 秒表，可以计小时分钟和秒钟，可以有暂停功能-Stopwatch, you can count the hours, minutes and seconds, you can pause
STC_115200
- 用STC 分频器产生波特率115200的串口通信-use STC to produce UART
4-bit
- VHDL CODE for 4 bit full adder through structural modelling.
EDA
- 用VHDL语言编写的各种小模块，有走马灯，计数器，循环寄存器等-VHDL language with a variety of small modules, there is a revolving door, counters, registers, and so the cycle