资源列表
vga_3bits
- 3位宽的vga接口的verilog代码，调试通过，在FPGA上可以综合。-3-bit wide vga interface verilog code, debugging through, can be integrated on the FPGA.
fpga
- fpga implementation of basic program
batch-26
- VHDL CODING FOR BASIC DIGITAL CIRCUITS
VHDL-divider-design
- VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-cr
RISC-Verification
- reduced instruction set of computer in verilog
Digital-stopwatch
- 数字秒表，用VHDL语言描述，用层次设计概念，将设计任务分成七个子模块，规定每一模块的功能和各模块之间的接口，然后再将各模块合起来形成顶层文件联试。-Digital stopwatch, using VHDL descr iption, level design concept, the design task is divided into seven sub-module to provide the interface between each module functions and m
MIPS-CPU
- 全指令集MIPS-CPU工程，包含各分模块工程、测试程序和详细设计文档，QuartusII7.2测试通过。-MIPS-CPU works full instruction set, contains the sub-module engineering, testing procedures and detailed design documents, QuartusII7.2, the test passes.
eeprom1
- EEPROM的VERILOG读写控制代码-Code of writting & reading control with EEPROM in Verilog HDL
v5gtp_sdi_drp_control
- xilinx virtex5 sdi drp 控制-xilinx virtex5 sdi drp control
lab14
- DE2平台上实现的数字钟，包含时、分、秒的24小时制时间系统，有校时，准点报时，整点广播等功能。-DE2 platform digital clock, contains, minutes, seconds, 24-hour time system, school, prospective point of time, the whole point of broadcasting.
uart_receive5bytes
- C语言实现CPLD串口接受五个字节，有校验，检验无效不做处理，接续检测接受，注释详细。-C language CPLD five byte serial accept check, test invalid without processing, splice detection to accept detailed notes.
tmp
- NIOS的IP核设计，可以实现针对于RTL8019AS的10兆网络接口控制，可进一步实现FPGA嵌入式网络开发应用-NIOS IP core design, can be achieved for RTL8019AS 10 trillion network interface control, further development and application of FPGA embedded network