资源列表
clock
- 可以當電子時鐘，有計時、調時還可以設鬧鐘，並且有鬧鈴-When the electronic clock timing, tune while you set the alarm clock and alarm
Verilog_divid
- vhdl语言描述传统除法器，传统乘法器的改进，从原理到实现的传统除法器-vhdl language to describe the traditional divider, the improvement of traditional multiplier principle to achieve the traditional divider
test_goldschmidt.vhd
- code to test a goldschmidt divider-code to test a goldschmidt divider
RSA
- programme qui decrit l algorithme de chiffremment RSA
THE-FIR-Base-on-FPGA
- 基于fpga的FIR滤波器实现，程序为11阶滤波器实现的源代码-Fpga-based FIR filter implementation, the source code
division-by-convergence
- a code for goldschmidt divider-a code for goldschmidt divider....
simple-divider
- simple divider vhdl code
triple_sdi_rx
- XILINX VIRTEX5 triple_SDI接受端-XILINX VIRTEX5 triple_SDI receiving end
ENDAT
- 一个用于接收ENDATA2.1协议的接口程序，经过测试该程序运行正确-One for receiving ENDAT 2.1 protocol interface program, tested the program runs correctly
assignment-1-(2)
- verilog coding of basic concept
DS18B20_NEW2
- DS18B20 FPGA 数字温度计-DS18B20 FPGA digital temperature
EMAC6
- verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。-verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well a