资源列表
altera-verilog
- 基于fpga的vga图片显示verilog代码-Display verilog code fpga vga picture
rom_dds
- this the code of Rom DDS-this is the code of Rom DDS
ARM_CY3
- 集合了CYCLONE 3系列功能 完成了窗口 spi adc dac等功能的程序 -Collection program CYCLONE 3 series feature complete window spi adc dac function
VHDL-32bit-add
- 功能实现：“1015+1016+1017+...+1115” 101个数的累加（1s/次） 数码管显示结果，结果为1015、2031、3048、40-The functions: " 1015+1016+1017+ the ...+1115" 101 the number of cumulative (1s/time) digital tube display results, results 1015,2031,3048,4066 ...
vga.v
- 基于altera公司的maxii epm240t100c5系列的 实现了 vgA接口控制-Based on the the altera Company' s maxii epm240t100c5 series realized vgA interface control
HiSPi_receiver_v4.0_XP2
- 支持美光HiSpi串行接口转12并行数据输出的FPGA程序-a project that support Hispi protocl
DE2_mt9m111-
- DE2_mt9m111例程 视频图像采集模块-DE2_mt9m111 routine video image acquisition module
DDS_AD9854_For_FPGA
- DDS_AD9854_for FPGA ,FPGA开发下的verilog源代码，信号发生器-DDS_AD9854_for FPGA, verilog source code, signal generator.
zuihou
- 数字时钟，有校正、闹钟、复位灯一些功能-Digital clock, correction, some of the features of the alarm clock, reset lamp! ! ! ! !
Ptxd
- 模拟RS-232串口产生周期串口数据，可以根据需要修改周期参数，及时钟参数，代码可以直接用来产生需要波特率的通讯模拟数据。-Analog RS-232 serial port generates cycle serial data, based on the need to modify the cycle parameters, and clock parameters, the code can be directly used to generate analog data communi
jiaozhi_1024
- 用VHDL语言实现按字节交织，交织深度为4.每组256字节-Block interleaver
dab1814114c3
- 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Descr iption ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route