资源列表
Using-Behavioural-Style
- vhdl code for implementation of multiplexer and demultiplexer on fpga
Bch15_5
- The attached file consists of implimentation of BCH codes in VHDL programming using XILINX software. This code will reduce the no. of gates requirement.
autoConter
- 基于quartusII的自动售票机电路图-Based on the vending machine circuit quartusII
rtl
- spi Flash控制器，适用于S25FL系列，欢迎下载-spi Flash controller for S25FL series, welcome to download
user_logic_Open_I2C
- iic implementation,用verilog实现了IIC标准协议的功能-iic implementation, verilog achieved using standard protocols IIC function
exemple_fifo_GradHori
- example filtre, framer-example filtre, framer..
key7seg
- key and 7 segment display progra-key and 7 segment display programm
frequency_meter
- 简易频率计，能够测试0~10000KHz之间的脉冲信号频率，并显示在数码管上。利用了100KHz的脉冲作为基准信号。包含课程设计报告。-Simple frequency meter, to test pulses between 0 ~ 10000KHz signal frequency and displays in the digital pipe. Use 100KHz pulse as a reference signal. Includes curriculum design repo
generic_fifos.tar
- Generic FIFO, writen in verilog hdl
telphone
- 基于altera de2的电话计费器设计，通过数码管显示时间和费用。vhdl编写-Meter design based on the altera de2 the phone, through the digital display time and costs. vhdl prepared
spdif_verilog
- 数字音频接口spdif ip core，verilog语言编写，带有testbench-spdif verilog ip core
library-ieee
- Look up table in vhdl