资源列表
MC8051_IPcore
- 利用FPGA开发一个示波器源码程序，欢迎各位多多下载参考-FPGA development using an oscilloscope source program..
ISEexamples
- VHDL and Verilog design examples.-VHDL and Verilog design examples.
SCPack
- SCPack is best packer for you
SDRAMcontrollerdesignl
- The SDRAM Controller module makes you control SDRAM conveniently with easy interface input type
RTL_Viewer
- In this chapter, we will explain about function of the controller separated in two parts Individual designer side and SDRAM side-In this chapter, we will explain about function of the controller separated in two parts Individual designer side an
rd1020
- Synchronous DRAM (SDRAM) has become a mainstream memory of choice in embedded system memory design due to its speed, burst access and pipeline features. For high-end applications using processors such as Motorola MPC 8260 or Intel StrongArm, the
FPGA
- FPGA硬件接口设计一书中的源码，有参考意义。-FPGA
FPGAdesignFAQ
- fpga设计的常用问答解释等。有一定用处。-fpga design faq for learning. it is useful .
xge_mac_latest.tar
- Ethernet 10GE MAC 以太网10G的MAC Verilog代码实现-Ethernet 10GE MAC
ASIC
- 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从 设计的系统行为级描述或 RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真。在-This article describes the standard cell library based on deep sub-micron digital IC design flow automation. This process from the design of sy
std_logic_1164
- 这个包定义了vhdl标准,为设计者在使用数据类型时建立用于vhdl的互连模型。-This packages defines a standard for designers to use in describing the interconnection data types used in vhdl modeling.
std_logic_arith
- 一个用于转换设置，以及签署SMALL_INT，整数，STD_ULOGIC，STD_LOGIC和STD_LOGIC_VECTOR比较函数。-A set of arithemtic, conversion, and comparison functions for SIGNED, UNSIGNED, SMALL_INT, INTEGER,STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR.