资源列表
ser_fir
- 用verilog实现一个8阶的改进串行FIR低通滤波器，输入数据位宽为12比特,经符号扩展后变为13比特。-With verilog order to achieve an improvement of 8 serial FIR low-pass filter, the input data bit width of 12 bits by sign extension into a 13-bit after.
tiaozhi
- 使用vhdl完成了ask psk fsk的调制和解调-Completed using vhdl ask psk fsk modulation and demodulation
fpga
- vhdl和c编写，fpga结合单片机完成测频计的功能，fpga主要完成频率的测量并把数据发送给单片机，单片机控制12864液晶完成显示-vhdl and c preparation, fpga of the single chip to complete the function of frequency meter, fpga major to complete the measurement frequency and the data sent to the MCU, MCU contro
cpu
- fpga实现了简单的cpu，有三个指令，有加法，减法，移动三条指令-fpga to achieve a simple cpu, there are three directives, there is addition, subtraction, move three orders
ad574
- vhdl编写，完成了对ad芯片ad574的控制，并将转化的数据存于fpga的内部存储器中，然后在发送出去。-vhdl prepared, completed ad control chip ad574, and conversion of data stored in the fpga internal memory and then sent.
uart
- vhdl编写，完成了uart的接口设计，包括信号检测，判决等-vhdl prepared to complete the uart interface design, including signal detection, decision, etc.
dds
- vhdl编写，利用fpga完成了dds发生器的功能-vhdl prepared using fpga complete function generator dds
backlight
- 用6个发光管模拟6个汽车尾灯（左右各3个），用4个开关作为汽车控制信号,分别为：左拐、右拐、故障和刹车。 车匀速行驶时，6个汽车尾灯全灭；右拐时，车右边3个尾灯从左至右顺序亮灭；左拐时，车左边3个尾灯从右至左顺序亮灭；故障时车6个尾灯一起明灭闪烁；刹车时，6个尾灯全亮 -backlight ，turn on and down in orde!
voter
- 7人表决器，运用for语句实现，很简单，很实用！-7 voting machines, used for statements to achieve, very simple and very practical!
LED
- 按下列顺序无限循环移动彩灯显示电路，LED灯总数为8个，具体循环次序如下：1.D7,D3,其余灭，右移三次后全灭 2。D4,D0亮，其余灭，左移三次后全灭 3。D3,D4亮，其余灭，各向两边移三次后全灭 4，D7,D0亮，其余灭，各向中间移三次后全灭 -----上述灯移动的间隔为0.5s-In the following order infinite loop mobile lantern display circuit, LED lights total of 8, th
rtc
- real time clock using spartan3e fpga
verilog
- 里面包含了大量VHDL的源码程序，赶快下载来分析分析吧 希望对大家有用哈-Which contains a large number of VHDL source program to analyze the analysis quickly download it hope to be useful Kazakhstan...