资源列表
division_cordic
- verilog code for division based on cordic algorithm
BCD8
- BCD码十进制8位加法器，采用超前进位的方法-8-bit decimal BCD adder yards, using look-ahead approach
sram
- a verilog sram code. use it to manipulate sram on fpga
frediv
- EDA分频器代码vhdl例程，可用，方便理解-EDA divider vhdl code routines that can be used to facilitate the understanding of
delsig
- AD中用于调制解调的delta sigma一阶调制器-AD used for modulation and demodulation of the first order delta sigma modulator
JMUX2TO1_vhdl
- This source are usefull function in VHDL for Transfer MCU Data betwine FPGA 2 port 8bit s wide Mux -This source are usefull function in VHDL for Transfer MCU Data betwine FPGA 2 port 8bit s wide Mux
JSFP
- 奇数分频-此程序对输入频率sysclk有奇数（X）分频的功能-Odd frequency- this program has an odd number of input frequency sysclk (X) frequency function
VHDL
- 这个是基于一下的要求设计的：1、输入输出数据宽度为12位， 2、阶数为4阶段线性相位FIR滤波器， 3、类型为：低通。-This is based on what the requirements of the design: an input and output data width is 12, 2, the order of the four stages of linear phase FIR filters, 3, type: low pass
serialtoparellel
- Write a HDL Code to use as a serial to parallel converter
function
- How to use Function in verilog example using factorial and parity code.
alpha1_3_compensator
- 同為適用於1.8V轉1.3V必迴路 在1Mhz頻率下 RLC各為 25m 4.7u 10u 排除浮點數的int整數補償器 給有需要的同學作為參考-The same applies to 1.8V 1.3V will turn 1Mhz frequency RLC circuit at each 25m 4.7u 10u exclude floating point int integer compensation to needy students as a reference
counter_14uou
- Counter wikipediya information will help you to understand about this program-Counter wikipediya information will help you to understand about this program