资源列表
my_kmp_matching
- KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。-Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment
shuzizhong
- 数字钟，功能齐全，很多部分是有硬件做成的，调试已经成功。-Digital clock, complete functions, many sections are hardware made debugging has been successful.
traffic_light
- 模式可调交通灯。利用拨码开关，实现正常工作模式、test模式、紧急模式的切换。-Mode adjustable traffic lights. Using DIP switches, to achieve normal operating mode, test mode, emergency mode switch.
IP_-design-and-development
- 基于nios2的IP核设计，用于fpga嵌入式系统-Based on the nios2 the IP core design for fpga embedded system
FPGA
- FPGA说明书，包括接口说明以及各模块说明-Introduction of FPGA
spafhisiPS2
- FPGA PS2实验经验证使用过可以用的程序！欢迎下载！-FPGA PS2 proven experimental procedures can be used! Welcome to download!
mbtutorial
- This tutorial guides you through the process of using Xilinx Embedded Development Kit (EDK) software tools, in which this tutorial will use the Xilinx Platform Studio (XPS) tool to create a simple processor system and the process of adding a cust
success
- 各种FPGA初级入门程序（已调试通过），包括计数器、流水灯、7段数码管显示以及PS2键盘接口驱动，采用VHDL语言编写，适合初学者参考-Various FPGA primary entry procedures (already debugged), including the counter, water light, 7 segment LED display and PS2 keyboard interface driver, using VHDL language, suitable f
fpga
- Verilog HDl代码，学习一颗看一下
median
- median work on a principle by selecting median value in the matrix.matrix wil taken as 3*3 & 5*5
pacoblaze-2.2
- 和picoblaze完全兼容的mcu ip core
eda
- 用vhdl语言编写信号发生器,实现不同频率，不同幅度的方波，锯齿波。-signal generator based on vhdl